Logic Bug Detection and Localization Using Symbolic Quick Error Detection
نویسندگان
چکیده
منابع مشابه
Logic Bug Detection and Localization Using Symbolic Quick Error Detection
We present Symbolic Quick Error Detection (Symbolic QED), a structured approach for logic bug detection and localization which can be used both during pre-silicon design verification as well as post-silicon validation and debug. This new methodology leverages prior work on Quick Error Detection (QED) which has been demonstrated to drastically reduce the latency, in terms of the number of clock ...
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During post-silicon validation, manufactured integrated circuits are extensively tested in actual system environments to detect design bugs. Bug localization involves identification of a bug trace (a sequence of inputs that activates and detects the bug) and a hardware design block where the bug is located. Existing bug localization practices during post-silicon validation are mostly manual and...
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This document is a set of notes to go along with a poster summarizing a summer of work on the QED project. The poster is located at http://www.stanford.edu/~adebray/CURIS/adebray_qed_poster.pdf, and these annotations (the document you are reading) can be found at http://www.stanford.edu/~adebray/CURIS/annotations.pdf. The goal is to provide more comprehensive information to explain methodology,...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2018
ISSN: 0278-0070,1937-4151
DOI: 10.1109/tcad.2018.2834401